Date of Award

Spring 2003

Document Type

Thesis

Degree Name

Master of Science (MS)

Department

Electrical & Computer Engineering

Program/Concentration

Computer Engineering

Committee Director

Vijayan K. Asari

Committee Member

James F. Leathrum, Jr.

Committee Member

Min Song

Call Number for Print

Special Collections LD4331.E55 N51 2003

Abstract

Images captured by wide-angle cameras show barrel type spatial distortion due to wide-angle configuration of the camera lens where image regions farther from the center are compressed in a nonlinear fashion. The barrel distortion correction technique based on least squares estimation attempts to correct a distorted image by expanding it nonlinearly so that straight lines in the object space remain straight in the image space. The intensity value of a pixel in the expanded image is calculated by back mapping its position to the corresponding position in the distorted image and performing linear interpolation on the neighboring pixels. Distorted images are analyzed to calculate the expansion coefficients and back mapping coefficients of the forward-mapping and the back-mapping polynomials in the distortion correction algorithm. These values are unique for each camera.

Demands for faster correction of distorted images in various real time applications lead to the development of a dedicated hardware architecture that can provide a high throughput rate. An absolute pipelined architecture is designed to correct barrel distortion in images by partitioning the distortion correction algorithm into four main modules. The architecture includes a CORDIC based rectangular to polar coordinate transformation module, a back mapping module for nonlinear transformation of corrected image space to distorted image space, a CORDIC based polar to rectangular coordinate transformation module, and a linear interpolation module to calculate the intensity of a pixel in the corrected image space. The system parameters include the expanded/corrected image size„ distorted image size, the back mapping coefficients, distortion center and the center of the corrected image. The hardware design is suitable for correcting 8-bit images of size up to four-million pixels. It can sustain a high throughput rate of 30 frames per second. The pipelined architecture design will facilitate the use of dedicated hardware that can be mounted along with the camera unit.

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DOI

10.25777/v4st-4s68

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