Date of Award

Summer 1984

Document Type

Thesis

Department

Electrical & Computer Engineering

Program/Concentration

Electrical Engineering

Committee Director

Meghanad D. Wagh

Committee Member

Damu Radhakrishnan

Committee Member

John W. Stoughton

Call Number for Print

Special Collections LD4331.E55S65

Abstract

Pipelining is now widely used in the design of high speed processors in order to overcome the intrinsic speed limitations imposed by the technology. For a good performance and avoidance of internal conflicts, the concurrent operations within different subunits of a pipeline architecture should be properly scheduled This scheduling problem is known to be intrinsically difficult" and a member of the "NP complete class of problems. The aim of this thesis is to develop heuristic suboptimal algorithms whose execution time is a polynomial function of the number of items to be scheduled. Insertion of delay is used as a basic tool for better utilization of hardware and thereby increasing the throughput at the expense of the execution time of an indivici1al data set. Rescheduling of pipelines made up of either single or many subunits communicating with each other are considered. Effects of unequal speeds and unequal loadings of the subunits are also studied. Results obtained compare well with earlier work.

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DOI

10.25777/rd16-6x76

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