Date of Award

Summer 1995

Document Type

Thesis

Degree Name

Master of Science (MS)

Department

Electrical & Computer Engineering

Program/Concentration

Electrical Engineering

Committee Director

James F. Leathrum, Jr.

Committee Member

John W. Stoughton

Committee Member

Martin D. Meyer

Call Number for Print

Special Collections LD4331.E55 T57

Abstract

Critical real-time applications require work to be completed before a predefined deadline, else the consequences may be catastrophic. The anticipation of faults in such systems necessitates the need for fault tolerance. Fault tolerance can be achieved in many different ways. A real-time system designer may impose restrictions on any of the system performance measures such as the latency, throughput and number of processors, depending on the type of application. In this work, several different fault tolerant strategies for any given DFG (Data Flow Graph) are discussed. DFG models are developed using the strategies and the resulting worst case performances a.re evaluated. A comparison of the different strategics is made to demonstrate the differences in performance. Such a comparison allows a designer to select a strategy to suit his application.

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DOI

10.25777/gt4n-s251

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