Polarization of Bi 2 Te 3 Thin Film in a Floating-Gate Capacitor Structure

Metal-Oxide-Semiconductor (MOS) capacitors with Bi2Te3 thin film sandwiched and embedded inside the oxide layer have been fabricated and studied. The capacitors exhibit ferroelectric-like hysteresis which is a result of the robust, reversible polarization of the Bi2Te3 thin film while the gate voltage sweeps. The temperature-dependent capacitance measurement indicates that the activation energy is about 0.33 eV for separating the electron and hole pairs in the bulk of Bi2Te3, and driving them to either the top or bottom surface of the thin film. Because of the fast polarization speed, potentially excellent endurance, and the complementary metal–oxide–semiconductor compatibility, the Bi2Te3 embedded MOS structures are very interesting for memory application.

Topological insulators (TIs) are materials that have an insulator (or semiconductor) bulk and gapless surfaces which are protected by time reversal symmetry. 1These materials have a Dirac cone at the surface that can be detected by angle resolved photo emission spectroscope (ARPES). 2,3he electrons at the TI surface can be considered as massless Dirac fermions. 4,5Therefore, carriers in these surface states have fast response and high mobility. 6The robustness of the TI surface states is protected by time reversal symmetry and is resistant to external perturbations such as defects and electric field. 7][10][11] They found that different quantum states can coexist in the surface and can be changed by external magnetic field which breaks the time reversal symmetry.However, these studies were mostly based on theoretical approach, delicate surface characterization method (e.g., ARPES), or scanning tunneling microscopy (STM).There is limited progress in the study of device applications.It would be very important and interesting to study how the TI materials behave in a device structure.We have previously reported a study of highperformance TI nanowire field effect transistor (FET) in which the TI materials acted as a conducting medium. 12ETs based on topological crystalline insulator SnTe thin film have also been recently demonstrated. 13Besides the emerging interests in TI, typical TI materials such as Bi 2 Te 3 have also attracted a lot of attention as thermoelectric material. 14However, the study of floating-gate structure in which TI materials are surrounded by dielectric has not yet been reported.It would be very interesting to see how the TI materials behave with a vertical electric field across them, as well as how they act as an information storage medium.
Information storage is of great interest in microelectronics.It is well recognized that the future information technology relies on novel electrically accessible non-volatile memory (NVM) with high speed and high density. 15][18][19] Among them, ferroelectric NVM is very attractive for its low power consumption, fast write/erase and good endurance. 11owever, the conventional perovskite ferroelectric materials are disadvantageous for low storage density and high integration cost. 20,21n this work, we fabricated Metal-Oxide-Semiconductor (MOS) capacitors with a Bi 2 Te 3 thin film sandwiched by two oxide layers.The Bi 2 Te 3 film acts as a "floating gate" similar to the poly-Si floating gate in a FLASH memory.We have studied the polarization of the Bi 2 Te 3 thin film for memory application.Such a hybrid MOS structure is very interesting for information storage and can also provide a good platform to study the properties of TI materials.
The schematic of the MOS capacitor structure is shown in Fig. 1(a).The Bi 2 Te 3 film was inserted in between the SiO 2 and Al 2 O 3 , forming a metal/Al 2 O 3 /Bi 2 Te 3 /SiO 2 /Si (MABOS) capacitor structure.The fabrication of these MABOS capacitors followed a conventional photolithographic procedure.The substrate is low doped (doping concentration about 10 15 cm À3 ) n-type Si wafers with 300 nm thermally grown SiO 2 .First, an active area (100 lm Â 100 lm, 50 lm Â 50 lm, 25 lm Â 25 lm, or 10 lm Â 10 lm) was defined by etching through the 300 nm SiO 2 on n-Si wafers.The wafers were then oxidized at 900 C for 22 min to achieve 11 nm dry SiO 2 .The dry oxide was thinned down to 6 nm by 2% HF etch for a) Authors to whom correspondence should be addressed.Electronic addresses: hyuan@gmu.eduand qli6@gmu.eduThe detail ALD conditions for Bi 2 Te 3 and Al 2 O 3 are as following.The Bi 2 Te 3 thin films were synthesized using bismuth trichloride (BiCl 3 ) and (trimethylsilyl) telluride ((Me 3 Si) 2 Te) as ALD precursors.The growth temperature was 170 C. The BiCl 3 precursor was volatilized at a temperature of 140 C, and the Te precursor was heated at 45 C. Furthermore, 10 sccm of N 2 was used as a carrier gas flow for the precursors.The ALD reaction chamber base pressure was kept at 40 mTorr (5.33 Pa).The deposition of Al 2 O 3 thin film followed a conventional ALD procedure which uses trimethylaluminum (TMA, Al(CH 3 ) 3 ) and O 2 plasma as precursors.The growth temperature was 300 C. N 2 was used as a carrier gas and the ALD reaction chamber base pressure was kept at 20 mTorr (2.67 Pa).
The resulting devices were first characterized with the transmission electron microscopy (TEM).The TEM image of the MOS capacitor cross-section (shown in Fig. 1(b)) indicates that the Bi 2 Te 3 is poly-crystalline.Atomic force microscopic (AFM) image of the Bi 2 Te 3 film grown by ALD on SiO 2 is shown in Fig. 1(c).It clearly shows that the Bi 2 Te 3 is poly-crystalline, and the film is uniform with a smooth surface.The whole process we used is compatible with complementary MOS (CMOS) technology, which provides a smooth transition to the application in microelectronics.
Then, capacitance-voltage (C-V) characterization was carried out by using an impedance analyzer (Agilent V R E4980A Precision LCR Meter) and a vacuum probe station (Lake Shore V R FWPX Cryogenic Probe Station).During the measurement, the samples were kept in 4 Â 10 À7 Torr (5.33 Â 10 À5 Pa) vacuum.Fig. 2 shows the C-V characteristics of MABOS capacitors with an area of 100 lm Â 100 lm.The C-V measurement was carried out at 1 MHz.These capacitors exhibit a hysteresis in C-V characteristics at room temperature.The hysteresis has a same direction of ferroelectric base capacitors. 22,23s shown in Fig. 2(a), the flat-band voltage (V FB ) of the C-V curve shifted to positive direction as the gate voltage was scanned from negative to positive.The hysteresis is larger when a larger range of gate voltage was scanned.But the hysteresis did not disappear even during a lowest voltage scan.The same hysteresis also shows in the MABOS capacitors with smaller area.
The hysteresis of MABOS capacitors is different from the hysteresis of a floating-gate memory cell.First, this hysteresis shift direction is opposite to that of a floating-gate memory device based on charge-trapping mechanism. 24,25s shown in inset of Fig. 2(a), in a floating-gate memory cell, positive charges (holes) will tunnel from Si into the floating gate after gate voltage sweeps from negative to positive, resulting in V FB shift to negative.Second, the hysteresis of MABOS capacitors exists in all sweep ranges, even in a small voltage sweep range from À3 V to 3 V.This is different from the charge-trapping devices in which the hysteresis is present only when gate voltage exceeds tunneling threshold voltage. 23,26n these MABOS capacitor devices, 6 nm SiO 2 is thick enough to prevent the electron/hole tunneling between the Bi 2 Te 3 and Si at such a low electric field.Even in the worst case that a small amount of charges tunnel through the 6 nm SiO 2 , the hysteresis shift should be in the opposite direction as mentioned above.Also, the Al 2 O 3 layer is about 30 nm, thick enough to block the charge transfer between Bi 2 Te 3 and the top gate metal.Therefore, the hysteresis shift must be resulted by the polarization of Bi 2 Te 3 film.In detail, the polarization is a result of charge accumulation on the two surfaces of Bi 2 Te 3 : the electrons and holes within the Bi 2 Te 3 film are separated and driven by the electric field, and then are accumulated on either surface of the Bi 2 Te 3 film, building an internal electrical field in the opposite direction to the external electrical field.This is quite similar to the polarization of metals and semiconductors in an electrical field.
The movement of carriers is much faster than the displacement of atoms/ions in the ferroelectric materials.The polarization shown in the C-V hysteresis is a result of accumulation of charge carriers on the surfaces.Unlike ferroelectrics where the polarization is due to the displacement of ions in the crystal, the polarization of Bi 2 Te 3 film is induced by the accumulation of carriers (electrons and holes).Therefore, the polarization of the Bi 2 Te 3 film in the MABOS structure should be much faster than that of normal ferroelectric films.Also, compared to the ion displacement in conventional ferroelectric materials, the electron movement should have less damage on the materials, leading to better device endurance.
To extract the polarization of Bi 2 Te 3 , we estimated the capacitance of dielectric layers based on the conventional model of MOS capacitor at high frequency.We can consider the polarized Bi 2 Te 3 as a parallel-plate capacitor with opposite polarized carriers (electrons or holes) on each surface.So, the capacitance of insulating layers (C INS ) can be obtained from the capacitance in accumulation region (100 lm Â 100 lm capacitors), that is Because the capacitance was measured with a small signal method at a high frequency, the transient polarized charges do not contribute to the total capacitance.However, this charge separation (or polarization) shifts V FB of the MABOS capacitor to negative or positive directions so that the hysteresis in the C-V measurement appears.The value of the applied gate voltages at the same capacitance in forward and reverse sweep directions can be obtained.As discussed above, the difference between these two gate voltage values (DV G ) is due to the difference in polarization (DP) of Bi 2 Te 3 between the two sweep directions.Their relationship can be expressed as Here, DQ P stands for the difference in polarized charges between two sweep directions, A for area of the capacitor, and the capacitance of Bi 2 Te 3 (C Bi 2 Te 3 ¼ 6.07 pF) is calculated from the total insulator capacitance which is assumed to be the total capacitance of SiO 2 , Bi 2 Te 3 , and Al 2 O 3 in serial.The memory window DV FB is equal to the DV G when the capacitance is equal to the flat band capacitance (C FB ).C FB can be expressed as 27 where the flat-band condition capacitance of Si (C SFB ) is the capacitance of Si (C S ) at flat-band condition, k n is the depletion width in Si at flat-band condition, A is the area of the capacitor, N D is the doping concentration (¼10 15 cm À3 ), e S and e 0 are Si relative permittivity and vacuum permittivity, respectively.We have performed temperature-dependent C-V characterization to study the polarization formation.The sample was measured at temperatures from 80 K to 290 K.As shown in Fig. 3, the hysteresis decreases as the temperature decreases.Below 250 K, the hysteresis is very small, almost negligible (Fig. 3(d)).At each temperature, the C-V curves measured at different frequencies are approximately the same.Also, the hysteresis of the C-V curves at different frequencies is the same.This indicates that there is negligible frequencydependence in the C-V measurement when frequency 1 MHz.In addition, the devices have been repeatedly tested for many times over a long period of duration (>6 months).The measured results are very reproducible in all these tests.The devices exhibit better programming/erasing characteristics than conventional poly-Si Flash memory (1 Â 10 6 cycles).This is because the polarization of surface state in Bi 2 Te 3 causes much less damage than hot-electron injection in conventional Flash memory cells.
where DP 0 is a fitting parameter, and qU B is the activation energy.Fig. 4(b) clearly shows that the DV FB exponentially decreases with 1=k B T. We can extract the value of qU B as 0.33 eV from linear fitting of lnðDV FB Þ versus 1=k B T. This relationship between DV FB and temperature indicates the carriers were thermally activated from surface state to bulk; and they were separated and accumulated on each surface when an external electric field was applied.
In addition, we have also fabricated and measured MOS capacitors with different thickness of Bi 2 Te 3 .We found that The memory window is shrunk as the temperature decreases, indicating that the remnant polarization becomes smaller at lower temperature.The memory window is fitted as an exponential function of 1/k B T (k B T is the thermal activation energy), agreeing well with both the linear-and log-scale experimental data.The activation energy is 0.33 eV according to the fitting.
MOS capacitors with Bi 2 Te 3 thinner than 15 nm did not exhibit significant hysteresis.It seems that the thin Bi 2 Te 3 in the capacitor behaves as a conductor.On the other hand, thick Bi 2 Te 3 will significantly decrease the electric field across it, resulting in small polarization and memory window.
In summary, we have fabricated and characterized floating-gate-like MOS capacitors with a topological insulator (Bi 2 Te 3 ) thin film sandwiched between insulating dielectric layers.The capacitors exhibited ferroelectric-like hysteresis.We have fully characterized and analyzed the hysteresis, and confirmed that it was a result of the polarization of Bi 2 Te 3 under vertical electric field.Also, the polarization was identified as a result of carrier separation under vertical electric field, which is different with ferroelectrics.The thermal activation energy for the carriers (electron and hole) to separate and accumulate at the top and bottom surface of Bi 2 Te 3 was extracted to be 0.33 eV which happens to be two times of the energy band gap of Bi 2 Te 3 .Due to the fast polarization speed and excellent endurance insured by the protected surface states, as well as the CMOS compatibility, the Bi 2 Te 3 embedded MOS structures are very interesting for memory application.Besides, this work demonstrated that the floating-gate capacitor structure is an effective platform to study the properties of topological insulator thin films.This work was supported by US NIST Grant No. 60NANB11D148 and US NSF Grant No. ECCS-0846649.
Research performed in part at the NIST Center for Nanoscale Science and Technology.We identify certain commercial equipment, instruments, or materials in this article to specify adequately the experimental procedure.In no case does such identification imply recommendation or endorsement by the National Institute of Standards and Technology, nor does it imply that the materials or equipment identified are necessarily the best available for the purpose.
0003-6951/2014/105(23)/233505/5/$30.00 V C 2014 AIP Publishing LLC 105, 233505-1 60 s.Then, atomic layer deposition (ALD) was used to deposit 30 nm Bi 2 Te 3 and 30 nm Al 2 O 3 on the samples followed by the formation of top Al gate.The extra Bi 2 Te 3 , Al 2 O 3 , and Al top gate beyond the active region were removed by ion mill before electrical measurement.Finally, the samples were annealed at 300 C in Ar by rapid thermal annealing (RTA).

FIG. 1 .
FIG. 1.(a) Schematic of the capacitor with Al/Al 2 O 3 /Bi 2 Te 3 /SiO 2 /Si structure.(b) High-resolution transmission electron microscopy (HRTEM) image of the capacitor cross-section.The scale bar is 5 nm in the image.The rectangular HRTEM image (10 nm Â 5 nm) on the right is an amplification of the Bi 2 Te 3 film within the red rectangle on the left image, showing the polycrystalline structure in the film.(c) AFM image of Bi 2 Te 3 film grown on SiO 2 with OH-hydroxyl groups by ALD.

Fig. 2 (
Fig. 2(b) shows the DP at different electric field.To calculate the electric field, a standard MOS capacitor with the same insulating layer capacitance (the capacitances of Al 2 O 3 , Bi 2 Te 3 , and SiO 2 in series, %4.6 pF) and doping concentration (1 Â 10 15 cm À3 ) as the measured capacitors was designed for simulation.The applied voltage of the standard MOS capacitor is recorded at the same value of capacitance measured in the experiment.This recorded voltage is over flat band voltage, i.e., gate voltage (V G ) À flat band voltage (V FB ).The net voltage drop across Bi 2 Te 3 , V BT , which is partial of ðV G À V FB Þ, can be extracted from the serial capacitor model.The electric field is V BT divided by the thickness of Bi 2 Te 3 .We extract the DP in the transition region between depletion and accumulation where the capacitance exhibits largest change with applied voltage.In the depletion or accumulation region where the measured capacitance only changes slightly with the applied voltage, the extraction of the DP would be inaccurate.The result indicated that the DP is largest around the flat-band voltage when the voltage drop across Bi 2 Te 3 is small.The memory window DV FB is equal to the DV G when the capacitance is equal to the flat band capacitance (C FB ).C FB can be expressed as27

FIG. 2 .
FIG. 2. (a) Capacitance-Voltage (C-V) characteristics of the Bi 2 Te 3 capacitor structure at 1 MHz with different voltage sweep ranges.The area of the capacitor is 100 lm Â 100 lm.(b) The changes in polarization versus the electric field at room temperature.(c) Illustration of the charge separation and polarization of Bi 2 Te 3 when an external field is applied.

Fig. 4 (
a) showed that DP changes with electric field at different temperatures.The largest value of DP always shows at around flat-band voltage.The DP decreases as the temperature decreases and finally disappears below 250 K. Fig. 4(b) shows the memory window (DV FB ) changes versus the temperature.The quantitative analysis of polarization of Bi 2 Te 3 indicates thermal activation of the surface carriers is the origin of polarization.In this case, DV FB can be written as