SMIMD - A Synchronous Multiple Instruction Multiple Data Computer Architecture

Date of Award


Document Type


Degree Name

Master of Science (MS)


Computer Science

Committee Director

Chester E. Grosch

Committee Member

Mohammad Zubair

Committee Member

Ravi Mukkamala

Call Number for Print

Special Collections LD4331.C65R62


This thesis assesses the feasibility of utilizing a hypercube interconnect topology to link a heterogeneous processor array in a very long instruction word (VLIW) computer architecture. The research focused upon the selection of a suitable arrangement of processors for the computer and the subsequent demonstration of the architecture's capability to handle simple loop iterations. Previous attempts at VLIW computer design are summarized, the new SMIMD architecture is presented, and suggestions for future research are given. The thesis concludes with results of the initial performance evaluations of the architecture design.


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