Date of Award

Spring 2019

Document Type


Degree Name

Master of Science (MS)


Computer Science

Committee Director

Mohommed Zubair

Committee Member

Yaohang Li

Committee Member

Ravi Mukkamala


Portability, an oftentimes sought-after goal in scientific applications, confers a number of possible advantages onto computer code. Portable code will often have greater longevity, enjoy a broader ecosystem, appeal to a wider variety of application developers, and by definition will run on more systems than its pigeonholed counterpart. These advantages come at a cost, however, and a rational approach to balancing costs and benefits requires a systemic evaluation. While the benefits for each application are likely situation-dependent, the costs in terms of resources, including but not limited to time, money, computational power, and memory requirements, are quantifiable. This document will identify strategies for enhancing performance portability on a variety of platforms available to the scientific computing community which will have little or no adverse impact on alternate architectures; this is done by implementing an iterative point solver requiring a high degree of data transfer bandwidth of a type commonly used in high performance applications used for computing a solution to partial differential equations (PDEs). In this thesis, we were able to show significant speed enhancements for architectures as diverse as complex traditional Central Processing Units (CPUs), Graphical Processing Units (GPUs), and Field Programmable Gate Arrays (FPGAs). Employing generalized optimizations on a variety of development frameworks we were able to show as much as a 92.5% reduction on a pipelined architecture (FPGA) while having a negligible impact on alternate architectures, and an 88.6% reduction in execution time on a Single Instruction Multiple Data (SIMD) architecture (GPU/CPU) while also having a negligible impact on alternate architectures. By enforcing these design rules in released versions of scientific code, the code has the potential to be optimally positioned for future advancements in computing architecture as well as being performance portable among existing architectures.


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