Date of Award

Fall 1983

Document Type

Thesis

Degree Name

Master of Science (MS)

Department

Electrical & Computer Engineering

Program/Concentration

Electrical Engineering

Committee Director

Meghanad D. Wagh

Committee Member

John W. Stoughton

Committee Member

Sherad Kanetkar

Abstract

This thesis explores the time optimal implementation of computational graphs on a finite register machine. The implementation fully exploits the machine architecture, especially, the number of registers. The derived algorithms allow one to obtain time efficient implementations of a given graph in machines with a known number of registers.

These optimization procedures are applied to digital signal processing graphs. It is shown that the regular structure of these graphs allows one to identify computational kernels which, when used repeatedly, can cover the entire graph. The l- and r-register implementations of Hadamard and Fast Fourier Transforms using various computational kernels are studied for their code sizes and time complexities. The results obtained also allow one to select an optimal hardware devoted to a particular computational application

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DOI

10.25777/zkjm-z906

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