Date of Award

Spring 2016

Document Type


Degree Name

Master of Science (MS)


Electrical & Computer Engineering

Committee Director

Lee A. Belfore, II

Committee Member

Oscar R. Gonzalez

Committee Member

ChunSheng Xin


The Input Decoupled Partially Adiabatic Logic (IDPAL) family was developed by Cutitaru to consume less power than other logic families as well as producing a resistance to side-channel attacks. With modifications made to IDPAL, the side-channel attack resistance is being revisited and quantified. The three logic families are compared in the work are CMOS, 2N2P, and IDPAL. An AND/NAND gate was created using each logic family and compared with two tests: 1) a simulated side-channel attack and 2) an energy analysis. In this work, a side-channel attack is the ability to predict the inputs of a logic circuit based on the electrical current waveform. For the Test 1, a higher prediction error suggests a higher resistance to attack. IDPAL produced the highest error in this test at 50.000%, which is 40.625% higher than in CMOS and 28.125% higher than in 2N2P. In Test 2, two primary statistics that were observed the variance in current trace (NSD and NED). Lower values of these measures implies a higher chance of a model resisting a side-channel attack. For the individual logic gates, the IDPAL model showed a lower variance in one of the two measures. For the Kogge-Stone adder, a more complex circuit, the IDPAL model was superior in both tests. With the results of the small and larger scale experiments in agreement, the final conclusion is that IDPAL does, indeed, resist side-channel attacks in a stronger fashion than other logic families.


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