Document Type
Article
Publication Date
1999
DOI
10.1155/1999/79875
Publication Title
VLSI Design
Volume
9
Issue
1
Pages
83-90
Abstract
We present novel asynchronous VLSI comparator schemes which are based on recently proposed reconfigurable shift switch logic and the traditional (precharged) CMOS domino logic. The schemes always produce a semaphore as a by-product of the process to indicate the end of domino process, which requires no additional delay and a minimal number of additional devices. For a large percentage of inputs the computations are much faster than traditional synchronous comparators due to the full utilization of the inherent speed of the circuits. Also the schemes are simple, area compact and stable.
Original Publication Citation
Lin, R., & Olariu, S. (1999). Reconfigurable shift switching parallel comparators. Vlsi Design, 9(1), 83-90. doi: 10.1155/1999/79875
Repository Citation
Lin, R., & Olariu, S. (1999). Reconfigurable shift switching parallel comparators. Vlsi Design, 9(1), 83-90. doi: 10.1155/1999/79875