Document Type
Article
Publication Date
1996
DOI
10.1155/1996/40175
Publication Title
VLSI Design
Volume
4
Issue
1
Pages
33-40
Abstract
The compaction step of integrated circuit design motivates associating several kinds of graphs with a collection of non-overlapping rectangles in the plane. These graphs are intended to capture various visibility relations amongst the rectangles in the collection. The contribution of this paper is to propose time- and cost-optimal algorithms to construct two such graphs, namely, the dominance graph (DG, for short) and the visibility graph (VG, for short). Specifically, we show that with a collection of n non-overlapping rectangles as input, both these structures can be constructed in θ (log n) time using n processors in the CREW model.
Original Publication Citation
Bhagavathi, D., Gurla, H., Olariu, S., Schwing, J.L., & Zhang, J. (1996). Time- and cost-optimal parallel algorithms for the dominance and visibility graphs. Vlsi Design, 4(1), 33-40. doi: 10.1155/1996/40175
Repository Citation
Bhagavathi, D., Gurla, H., Olariu, S., Schwing, J.L., & Zhang, J. (1996). Time- and cost-optimal parallel algorithms for the dominance and visibility graphs. Vlsi Design, 4(1), 33-40. doi: 10.1155/1996/40175
