Date of Award

Summer 1995

Document Type

Thesis

Degree Name

Master of Science (MS)

Department

Electrical & Computer Engineering

Program/Concentration

Electrical Engineering

Committee Director

Martin D. Myer

Committee Member

James F. Leathrum

Committee Member

John W. Stoughton

Call Number for Print

Special Collections LD4331.E55A443

Abstract

A fault tolerant pipelined architecture for high sampling rate adaptive filters is presented in this thesis. The architecture is based on the computational requirements of delayed LMS and lattice adaptive 61ters. It offers robust performance in the presence of single hardware faults, and software faults resulting from numerical instability. Two different architectures are proposed. One allows a graceful degradation in system performance in the event of a fault, and the other uses a module replacement strategy to recover from faults without decreasing performance. Analysis of the steady state error increase due to filter reconfiguration is presented. The reliability of the proposed system is analyzed and compared to existing implementation strategies. Methods for fault detection, fault location and recovery via hardware reconfiguration are also discussed. Simulation results illustrating recovery from processor faults are presented.

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DOI

10.25777/ytw7-5484

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