Date of Award

Spring 1998

Document Type

Thesis

Degree Name

Master of Science (MS)

Department

Electrical & Computer Engineering

Program/Concentration

Computer Engineering

Committee Director

Martin D. Meyer

Committee Member

John W. Stockton

Committee Member

James F. Leathrum

Call Number for Print

Special Collections LD4331.E55 D56

Abstract

In this thesis, an 8-bit least mean squares (LMS) adaptive digital filter with 16 coefficients is implemented on a single FPGA, using the MaxPlus+2 design environment. The system is constructed as a hierarchical structure, using four different levels of design hierarchy. Subdesigns at each level of the hierarchy project are complied, fitted and simulated to test and verify their functional correctness. The complete system is tested and verified by checking the MaxPlus+2 simulator results against fixed-point integer arithmetic simulations written in Matlab. The resulting adaptive filter is subsequently mapped to the Alters FLEX I OK20TC144-3 device, resulting in a 14,500 gate equivalent circuit, with a minimum sampling interval of approximately 9.7us. Three curves that represent the relationship between the system parameters and the system performance are derived experimentally based on this approach and several modifications. These curves show that the relationship between equivalent gate count and the number of weights, N, is very similar to the relationship between equivalent gate count and the number of input bits, m. Results are also presented which describe the approximate relationship between the number of weights, N, and the resulting maximum sampling rate.

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DOI

10.25777/thxc-kn11

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