Date of Award

Fall 1985

Document Type

Thesis

Department

Electrical & Computer Engineering

Program/Concentration

Electrical Engineering

Committee Director

S. V. Ranetkar

Committee Member

John W. Stoughton

Committee Member

S. Zahorian

Call Number for Print

Special Collections LD4331.E55F44

Abstract

Interconnection topology and device performance are of major concern in the design of LSI/VLSI systems, Pass networks are very suitable in this regard because of low power consumption, high density, and simple interconnection topology. A special type of pass networks called Binary Tree Structured (BTS) pass networks uses almost minimum number of transistors for the design of switching circuits. An algorithmic procedure is developed here for BTS pass networks which is very efficient in terms of both execution time and memory space. Based on these networks, the necessary and sufficient conditions are derived for the design of multiple-output pass networks. A new kind of Programmable Logic Arrays (PLA) called pass logic PLA is also proposed in this thesis. Fault detection techniques for multiple-output pass networks with special attention given to multiple-output BTS pass networks are presented here. Finally, it is found that under certain conditions some of the faults which occur in pass networks cannot be detected.

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DOI

10.25777/3sg0-sr95

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