Date of Award

Summer 1985

Document Type

Thesis

Department

Electrical & Computer Engineering

Program/Concentration

Electrical Engineering

Committee Director

Griffith J. McRee

Committee Member

Jack B. Stoughton

Committee Member

Stephen A. Zahorian

Call Number for Print

Special Collections LD4331.E55M67

Abstract

A computer-aided design approach for the simplification of analog computer simulation is presented. The simulation configuration consists of an EAI 2000 analog computer with serial communications link to a PDP — 11/24 digital computer. Under control of the PDP-11, the analog simulations are realized with appropriate time and magnitude scaling which adjusts the range of the simulation coefficients and prevents overloads of the analog components. The analog computer hardware configuration accommodates both stable plants up to eighth order and closed-loop systems up to tenth order. Cascade compensation is provided for the closed-loop systems.

The plant may be described by either a transfer function, pole-zero locations, or a sum of first and second order sections. When given either of the first two descriptions, the PDP-11 software performs a partial fraction expansion. The plant is modeled in a modified diagonal or Jordan canonical form.

Scaling of the simulation is presented. Magnitude scaling of the simulation variables is based on the unit step response of the first and second order sections of the plant model. Time scaling is used to adjust the range of the coefficients used to realize the simulation on the analog computer.

Rights

In Copyright. URI: http://rightsstatements.org/vocab/InC/1.0/ This Item is protected by copyright and/or related rights. You are free to use this Item in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s).

DOI

10.25777/crw9-nz11

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