Date of Award

Spring 1985

Document Type

Thesis

Degree Name

Master of Science (MS)

Department

Electrical & Computer Engineering

Program/Concentration

Electrical Engineering

Committee Director

Damu Radhakrishnan

Committee Member

John W. Stoughton

Committee Member

S. V. Kanetkar

Call Number for Print

Special Collections LD4331.E55S52

Abstract

Testability criteria for stuck-open (s-op) faults in one-dimensional unilateral iterative logic arrays (ILA) of CMOS combinational cells are considered in this thesis. A functional fault model to represents-op faults i~ an ILA cell is given. The procedure to detect as-op fault needs a pair of test vectors. The first is used to set up the initial conditions required to test the fault and the second is the test which distinguishes between the good and the bad circuit. Based on this approach necessary and sufficient conditions are given for the testability of as-op fault in a CMOS ILA cell. These conditions are extended to include the C-testability for the s-op fault (testing an ILA by a constant number of tests independent of the length of the array). Since some of the tests will be invalidated due to the delays in input changes, additional requirements to be satisfied for the generation of valid test vectors are proposed.

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DOI

10.25777/y4bv-x626

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